1. Field of the Invention
Embodiments of the invention generally relate to methods for depositing capping layers within a semiconductor feature, and more particularly for electrolessly depositing doped metal alloys on conductive surfaces.
2. Description of the Related Art
Recent improvements in circuitry of ultra-large scale integration (ULSI) on substrates indicate that future generations of integrated circuit (IC) semiconductor devices will require smaller multi-level metallization. The multilevel interconnects that lie at the heart of this technology require planarization of interconnects formed in high aspect ratio features, including contacts, vias, lines and other features. Reliable formation of these interconnects is very important to the success of ULSI and to the continued effort to increase circuit density by decreasing the dimensions of semiconductor features and decreasing the widths of interconnects (e.g., lines) to 0.13 μm and less.
Currently, copper and its alloys have become the metals of choice for sub-micron interconnect technology because copper (Cu) has a lower resistivity than aluminum (Al) (i.e., 1.67 μΩ-cm for Cu as compared to 3.1 μΩ-cm for Al), a higher current carrying capacity, and significantly higher electromigration resistance. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Further, copper has a good thermal conductivity and is available in a highly pure state.
However, despite attributes Cu has over Al, as Cu interconnect lines decrease in dimension, the Cu interconnect is increasingly susceptible to diffusion and electromigration failure. Therefore, a liner barrier layer is used to encapsulate the Cu interconnect to prevent diffusion of Cu to adjacent dielectric layers. Also, Cu readily forms copper oxide when exposed to oxygen containing environments. Copper oxide formation increases the resistance of the Cu interconnect and reduces the reliability of the overall circuit.
One solution is to selectively deposit a metal alloy on the Cu interconnect which provides a barrier resistance to copper diffusion, electromigration and oxidation. Copper electromigration in damascene interconnections can be significantly reduced by replacing the top Cu/dielectric interface with a Cu/metal interface by depositing a thin metal capping layer of, for example, cobalt tungsten phosphorus (CoWP), cobalt tin phosphorus (CoSnP), and cobalt tungsten phosphorus boron (CoWPB), onto the surface of the Cu interconnect. In addition, for increasing adhesion and selectively depositing the capping layer over the Cu interconnect, an activation layer such as palladium (Pd) or platinum (Pt) may be deposited on the surface of the Cu interconnection prior to depositing the capping layer.
However, with the increasing demand on IC performance and reliability, the resistance-capacitance (RC) delay constant of metal/dielectric systems (e.g., Cu/SiO2, Cu/SiCOH, Cu/SiCO, Cu/organic low k dielectric), due to the inherent resistance (R) and capacitance (C) of the materials used, will necessarily decrease to support future requirements. The anticipated RC delay constant reduction of about 30% to 50% of interconnects adjacent very low k dielectric materials having a low k constant less than about 2.5, including air gap technology (low k constant=1), requires metal capping layers to provide improved barrier resistance to both oxygen diffusion and copper diffusion. In addition, high processing temperatures reaching 400° C. to 450° C. for periods of about 8 hours during back-end-of-the-line (BEOL) layer processing and chip packaging lead to oxidation of Co alloys and Pd of the thin capping layers. In particular, oxidation is particularly detrimental in thinner capping layers having thicknesses of less than about 150 Å, for example a 70 Å layer of COWP or COWPB adjacent oxygen sources in the surrounding dielectric and/or air.
Therefore, there is a need for a method to forming a capping layer on a conductive surface of a semiconductor feature exhibiting improved barrier properties against oxygen and copper diffusion while maintaining low electrical resistance and excellent adhesion to the conductive surface.